1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to a waveform track-and-hold circuit that receives an analog input signal and generates an analog output signal under control of a logic control signal that identifies track operating phases and hold operating phases.
2. Description of Related Art
Waveform track-and-hold circuits, which are also known as "sample-and-hold" circuits, are most often used in association with analog-to-digital converters. Such circuits perform a sampling operation on continuous waveforms and then store the fetched value. In other words, waveform track-and-hold circuits perform input voltage tracking operations and store the corresponding value at the time instant when a control signal is applied. In general, waveform track-and-hold circuits have an analog input for the waveform to be sampled, an analog output, and a logic control input that receives a control signal (e.g., from a multiplexer). When the control signal is in a predetermined logic state (e.g., a high logic state), the waveform track-and-hold circuit behaves like a unitary gain linear amplifier or, if required, with a predetermined gain (i.e., the output waveform is a reproduction of the waveform at the analog input). The transition of the control signal from the high logic level to a low logic level enables a "hold" or storage phase.
FIG. 1 shows a conventional waveform track-and-hold circuit. The waveform track-and-hold circuit 1 includes an input buffer IB that receives the input voltage VIN (i.e., the signal to be sampled). The input buffer IB and an output buffer OB of the circuit are usually formed by emitter follower amplifiers. The output of the input buffer IB is supplied to a switch S, which is usually formed by a MOSFET transistor and controlled by a logic control signal VCK. A storage capacitor CH is then provided and followed by the output buffer OB, which supplies an output voltage VOUT (i.e., the waveform produced by the waveform track-and-hold circuit 1).
FIG. 1 also shows, in the form of an equivalent circuit, some undesired effects that are present in the conventional waveform track-and-hold circuit 1. A capacitance CS placed between the input of the logic control signal VCK and the input of the output buffer OB represents the "charge dump" effect that causes a raising of the voltage level stored during transition from the high logic signal to the low logic signal (i.e., a switch-over from the track phase to the hold phase).
A current generator IDR models the "droop rate" phenomenon, which is a reduction of the voltage value stored in the storage capacitor CH during the hold phase due to the small input current of the output buffer OB that slowly discharges the storage capacitor. A capacitor CFT represents the "feed-through" phenomenon, which is a charge injection during the hold phase that is due to the presence of parasitic capacitances in the transistor acting as the switch S. This also modifies the voltage value stored in the storage capacitor CH and directly reflects on the accuracy of a converter associated with the waveform track-and-hold circuit.
In order to overcome these drawbacks, it is known to employ differential structures such as those used in the waveform track-and-hold circuit 2 of FIG. 2. (In the following description, a differential circuit is defined as a circuit whose output signal depends on the difference of the input signals through a transfer function, such as an amplification ratio.) The waveform track-and-hold circuit 2 of FIG. 2 includes a differential input buffer DIB that receives both a positive input signal INP and a negative input signal INN. Two switches SP and SN receive the output signals OUTP' and OUTN' of the differential input buffer DIB and are followed by a first storage capacitor CI and a second storage capacitor C2, respectively. A differential output buffer DOB is provided downstream and produces two differential output signals OUTP and OUTN.
The "charge dump" effect is removed from the waveform track-and-hold circuit 2 of FIG. 2 because both switches SP and SN introduce the same charge amount (i.e., it is suppressed using differential output signals). Similarly, at least under a first approximation, the "droop rate" is equal for both differential output signals OUTP and OUTN, and so it is compensated. However, the "feed-through" issue remains, but it can be solved by connecting some capacitors between the collector of the transistor forming the differential stage of the differential input buffer DIB and the capacitor on the opposite output of the differential input stage DIB.
For example, in FIG. 2, the capacitor for the waveform track-and-hold circuit 2 is connected between the collector of the transistor whose base receives the output signal OUTP and the second storage capacitor C2. For further details, reference is made to an article by P. Vorenkamp and J. P. M. Verdaasdonk entitled "Fully Bipolar, 120-Msample/s 10-b Track-and-Hold Circuit" (IEEE Journal of Solid State Circuitry, vol. 27, No. 7, Jul. 1992), which is herein incorporated by reference.
However, conventional differential circuits of the type described above still have drawbacks. For example, they are not very flexible with respect to the type of control signal that can be sent, so it is difficult to drive the switches with CMOS signals without employing a CMOS-to-ECL signal converter. This may be a particular nuisance for hybrid circuits. Furthermore, additional capacitors are required to lower the feed-through during the hold phase. Additionally, the differential input stage is particularly sensitive to thermal drifts of the input transistors. This can lead to acquisition errors that are especially harmful if the waveform track-and-hold circuit is used for an analog-digital converter.